module tb_add;

reg clk;
reg rst_n;

always #10 clk = ~clk;

initial
	begin
		clk <= 1'b1;
		rst_n <= 1'b0;
		#10
		rst_n <= 1'b1;
	end

//rom
initial
	begin
		$readmemb("D:/desktop/risc_v/vivadio_tb/add_tb/add_tb.srcs/sim_1/imports/tb/inst_data_add.txt", tb_add.u_open_soc_tb_add1.u_rom_open_soc_1.rom_mem);
	end

initial
	begin
		while (1)
			begin
				@(posedge clk)
				$display("x27 value is %d", tb_add.u_open_soc_tb_add1.u_top_risc_open_soc_1.u_regs_top_risc_1.regs[27]);
				$display("x28 value is %d", tb_add.u_open_soc_tb_add1.u_top_risc_open_soc_1.u_regs_top_risc_1.regs[28]);
				$display("x29 value is %d", tb_add.u_open_soc_tb_add1.u_top_risc_open_soc_1.u_regs_top_risc_1.regs[29]);
				$display("-------------------------------------");
			end
	end

open_soc u_open_soc_tb_add1(
             .clk ( clk ),
             .rst_n ( rst_n )
         );

endmodule
